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f98ae1 |
GEN_IR_SRCS = \
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f98ae1 |
build/gen/ir/ir/gen_irio.c \
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f98ae1 |
build/gen/ir/ir/gen_irnode.c \
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a5e4b0 |
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a5e4b0 |
GEN_EMITTER_SRCS = \
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a5e4b0 |
build/gen/ir/be/arm/gen_arm_emitter.c \
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a5e4b0 |
build/gen/ir/be/amd64/gen_amd64_emitter.c \
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a5e4b0 |
build/gen/ir/be/ia32/gen_ia32_emitter.c \
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a5e4b0 |
build/gen/ir/be/sparc/gen_sparc_emitter.c \
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a5e4b0 |
build/gen/ir/be/TEMPLATE/gen_TEMPLATE_emitter.c \
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e685cd |
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e685cd |
GEN_OPCODES_SRCS = \
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e685cd |
build/gen/ir/be/arm/gen_arm_new_nodes.c \
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e685cd |
build/gen/ir/be/amd64/gen_amd64_new_nodes.c \
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e685cd |
build/gen/ir/be/ia32/gen_ia32_new_nodes.c \
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e685cd |
build/gen/ir/be/sparc/gen_sparc_new_nodes.c \
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e685cd |
build/gen/ir/be/TEMPLATE/gen_TEMPLATE_new_nodes.c \
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9b9d84 |
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9b9d84 |
GEN_REGALLOC_SRCS = \
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9b9d84 |
build/gen/ir/be/arm/gen_arm_regalloc_if.c \
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9b9d84 |
build/gen/ir/be/amd64/gen_amd64_regalloc_if.c \
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9b9d84 |
build/gen/ir/be/ia32/gen_ia32_regalloc_if.c \
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9b9d84 |
build/gen/ir/be/sparc/gen_sparc_regalloc_if.c \
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9b9d84 |
build/gen/ir/be/TEMPLATE/gen_TEMPLATE_regalloc_if.c \
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