Blame project/common.mk

cef05b
ir/%.lo:	build/gen/ir/%.c $(ALL_HEADERS) host.tag tree.tag gen.tag
cef05b
		$(CC) -c -o $@ $< $(CFLAGS_SHARED)
cef05b
cef05b
ir/%.o:		build/gen/ir/%.c $(ALL_HEADERS) host.tag tree.tag gen.tag
cef05b
		$(CC) -c -o $@ $< $(CFLAGS_STATIC)
cef05b
cef05b
ir/%.lo:	$(SOURCE_DIR)/ir/%.c $(ALL_HEADERS) host.tag tree.tag gen.tag
cef05b
		$(CC) -c -o $@ $< $(CFLAGS_SHARED)
cef05b
cef05b
ir/%.o:		$(SOURCE_DIR)/ir/%.c $(ALL_HEADERS) host.tag tree.tag gen.tag
cef05b
		$(CC) -c -o $@ $< $(CFLAGS_STATIC)
cef05b
f98ae1
GEN_IR_SRCS = \
f98ae1
	build/gen/ir/ir/gen_irio.c \
f98ae1
	build/gen/ir/ir/gen_irnode.c \
a5e4b0
a5e4b0
GEN_EMITTER_SRCS = \
a5e4b0
	build/gen/ir/be/arm/gen_arm_emitter.c \
a5e4b0
	build/gen/ir/be/amd64/gen_amd64_emitter.c \
a5e4b0
	build/gen/ir/be/ia32/gen_ia32_emitter.c \
a5e4b0
	build/gen/ir/be/sparc/gen_sparc_emitter.c \
a5e4b0
	build/gen/ir/be/TEMPLATE/gen_TEMPLATE_emitter.c \
e685cd
e685cd
GEN_OPCODES_SRCS = \
e685cd
	build/gen/ir/be/arm/gen_arm_new_nodes.c \
e685cd
	build/gen/ir/be/amd64/gen_amd64_new_nodes.c \
e685cd
	build/gen/ir/be/ia32/gen_ia32_new_nodes.c \
e685cd
	build/gen/ir/be/sparc/gen_sparc_new_nodes.c \
e685cd
	build/gen/ir/be/TEMPLATE/gen_TEMPLATE_new_nodes.c \
9b9d84
9b9d84
GEN_REGALLOC_SRCS = \
9b9d84
	build/gen/ir/be/arm/gen_arm_regalloc_if.c \
9b9d84
	build/gen/ir/be/amd64/gen_amd64_regalloc_if.c \
9b9d84
	build/gen/ir/be/ia32/gen_ia32_regalloc_if.c \
9b9d84
	build/gen/ir/be/sparc/gen_sparc_regalloc_if.c \
9b9d84
	build/gen/ir/be/TEMPLATE/gen_TEMPLATE_regalloc_if.c \
cef05b
cef05b
cef05b
be_src_dirs    = $(SOURCE_DIR)/ir/be/*/
cef05b
be_src_files   = $(addsuffix *.c,$(be_src_dirs))
cef05b
be_sort_files  = $(sort $(wildcard $(be_src_files)))
cef05b
cef05b
ir_src_dirs    = $(SOURCE_DIR)/ir/*/
cef05b
ir_src_files   = $(addsuffix *.c,$(ir_src_dirs))
cef05b
ir_sort_files  = $(sort $(wildcard $(ir_src_files)))
cef05b
cef05b
gen_src_files  = $(GEN_IR_SRCS)
cef05b
gen_src_files += $(GEN_EMITTER_SRCS)
cef05b
gen_src_files += $(GEN_OPCODES_SRCS)
cef05b
gen_src_files += $(GEN_REGALLOC_SRCS)
cef05b
cef05b
cef05b
BE_SRCS        = $(subst $(SOURCE_DIR)/ir/,ir/,$(be_sort_files))
cef05b
IR_SRCS        = $(subst $(SOURCE_DIR)/ir/,ir/,$(ir_sort_files))
cef05b
GEN_SRCS       = $(subst build/gen/ir/,ir/,$(gen_src_files))
cef05b
cef05b
COMMON_SRCS    = $(BE_SRCS) $(IR_SRCS) $(GEN_SRCS)
7fc87c
7fc87c
ir/common/firm.o:	version.tag
7fc87c
ir/common/firm.lo:	version.tag