Blame project/codegen.mk

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clean:		clean-gen
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clean-gen:
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		rm -f gen.tag
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		rm -f $(GEN_IR_SRCS)
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		rm -f $(GEN_IR_HEADERS)
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		rm -f $(GEN_EMITTER_SRCS)
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		rm -f $(GEN_EMITTER_HEADERS)
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		rm -f $(GEN_OPCODES_SRCS)
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		rm -f $(GEN_OPCODES_HEADERS)
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		rm -f $(GEN_REGALLOC_SRCS)
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		rm -f $(GEN_REGALLOC_HEADERS)
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		rm -f $(GEN_BE_DIR_ARM)/emitter.tag
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		rm -f $(GEN_BE_DIR_AMD64)/emitter.tag
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		rm -f $(GEN_BE_DIR_IA32)/emitter.tag
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		rm -f $(GEN_BE_DIR_SPARC)/emitter.tag
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		rm -f $(GEN_BE_DIR_TEMPLATE)/emitter.tag
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		rm -f $(GEN_BE_DIR_ARM)/opcodes.tag
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		rm -f $(GEN_BE_DIR_AMD64)/opcodes.tag
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		rm -f $(GEN_BE_DIR_IA32)/opcodes.tag
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		rm -f $(GEN_BE_DIR_SPARC)/opcodes.tag
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		rm -f $(GEN_BE_DIR_TEMPLATE)/opcodes.tag
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		rm -f $(GEN_BE_DIR_ARM)/regalloc.tag
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		rm -f $(GEN_BE_DIR_AMD64)/regalloc.tag
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		rm -f $(GEN_BE_DIR_IA32)/regalloc.tag
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		rm -f $(GEN_BE_DIR_SPARC)/regalloc.tag
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		rm -f $(GEN_BE_DIR_TEMPLATE)/regalloc.tag
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GEN_ALL 	= $(GEN_IR_SRCS) \
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		  $(GEN_IR_HEADERS) \
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		  $(GEN_EMITTER_SRCS) \
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		  $(GEN_EMITTER_HEADERS) \
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		  $(GEN_OPCODES_SRCS) \
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		  $(GEN_OPCODES_HEADERS) \
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		  $(GEN_REGALLOC_SRCS) \
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		  $(GEN_REGALLOC_HEADERS) \
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# build/gen/ir/be
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GEN_BE_DIR_ARM		= build/gen/ir/be/arm
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GEN_BE_DIR_AMD64	= build/gen/ir/be/amd64
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GEN_BE_DIR_IA32		= build/gen/ir/be/ia32
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GEN_BE_DIR_SPARC	= build/gen/ir/be/sparc
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GEN_BE_DIR_TEMPLATE	= build/gen/ir/be/TEMPLATE
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GEN_SPEC_ARM		= $(SOURCE_DIR)/ir/be/arm/arm_spec.pl
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GEN_SPEC_AMD64		= $(SOURCE_DIR)/ir/be/amd64/amd64_spec.pl
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GEN_SPEC_IA32		= $(SOURCE_DIR)/ir/be/ia32/ia32_spec.pl
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GEN_SPEC_SPARC		= $(SOURCE_DIR)/ir/be/sparc/sparc_spec.pl
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GEN_SPEC_TEMPLATE	= $(SOURCE_DIR)/ir/be/TEMPLATE/TEMPLATE_spec.pl
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# gen-ir
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GEN_IR_TOOL = $(SOURCE_DIR)/scripts/gen_ir.py
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GEN_IR_SPEC = $(SOURCE_DIR)/scripts/ir_spec.py
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build/gen/ir/ir/%.c:	$(SOURCE_DIR)/scripts/templates/%.c \
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			$(GEN_IR_TOOL) $(GEN_IR_SPEC) tree.tag
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	$(GEN_IR_TOOL) $(GEN_IR_SPEC) $< > $@
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build/gen/ir/ir/%.h:	$(SOURCE_DIR)/scripts/templates/%.h \
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			$(GEN_IR_TOOL) $(GEN_IR_SPEC) tree.tag
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	$(GEN_IR_TOOL) $(GEN_IR_SPEC) $< > $@
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build/gen/include/libfirm/nodes.h:	$(SOURCE_DIR)/scripts/templates/nodes.h \
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					$(GEN_IR_TOOL) $(GEN_IR_SPEC) tree.tag
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	$(GEN_IR_TOOL) $(GEN_IR_SPEC) $< > $@
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# gen-emitter
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GEN_EMITTER_TOOL = $(SOURCE_DIR)/ir/be/scripts/generate_emitter.pl
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$(GEN_BE_DIR_ARM)/emitter.tag:		$(GEN_EMITTER_TOOL) $(GEN_SPEC_ARM) tree.tag
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	$(GEN_EMITTER_TOOL) $(GEN_SPEC_ARM) $(GEN_BE_DIR_ARM)
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	touch $@
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$(GEN_BE_DIR_AMD64)/emitter.tag:	$(GEN_EMITTER_TOOL) $(GEN_SPEC_AMD64) tree.tag
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	$(GEN_EMITTER_TOOL) $(GEN_SPEC_AMD64) $(GEN_BE_DIR_AMD64)
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	touch $@
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$(GEN_BE_DIR_IA32)/emitter.tag:		$(GEN_EMITTER_TOOL) $(GEN_SPEC_IA32) tree.tag
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	$(GEN_EMITTER_TOOL) $(GEN_SPEC_IA32) $(GEN_BE_DIR_IA32)
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	touch $@
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$(GEN_BE_DIR_SPARC)/emitter.tag:	$(GEN_EMITTER_TOOL) $(GEN_SPEC_SPARC) tree.tag
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	$(GEN_EMITTER_TOOL) $(GEN_SPEC_SPARC) $(GEN_BE_DIR_SPARC)
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	touch $@
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$(GEN_BE_DIR_TEMPLATE)/emitter.tag:	$(GEN_EMITTER_TOOL) $(GEN_SPEC_TEMPLATE) tree.tag
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	$(GEN_EMITTER_TOOL) $(GEN_SPEC_TEMPLATE) $(GEN_BE_DIR_TEMPLATE)
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	touch $@
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$(GEN_BE_DIR_ARM)/gen_arm_emitter.c:		$(GEN_BE_DIR_ARM)/emitter.tag
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$(GEN_BE_DIR_ARM)/gen_arm_emitter.h:		$(GEN_BE_DIR_ARM)/emitter.tag
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$(GEN_BE_DIR_AMD64)/gen_amd64_emitter.c:	$(GEN_BE_DIR_AMD64)/emitter.tag
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$(GEN_BE_DIR_AMD64)/gen_amd64_emitter.h:	$(GEN_BE_DIR_AMD64)/emitter.tag
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$(GEN_BE_DIR_IA32)/gen_ia32_emitter.c:		$(GEN_BE_DIR_IA32)/emitter.tag
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$(GEN_BE_DIR_IA32)/gen_ia32_emitter.h:		$(GEN_BE_DIR_IA32)/emitter.tag
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$(GEN_BE_DIR_SPARC)/gen_sparc_emitter.c:	$(GEN_BE_DIR_SPARC)/emitter.tag
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$(GEN_BE_DIR_SPARC)/gen_sparc_emitter.h:	$(GEN_BE_DIR_SPARC)/emitter.tag
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$(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_emitter.c:	$(GEN_BE_DIR_TEMPLATE)/emitter.tag
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$(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_emitter.h:	$(GEN_BE_DIR_TEMPLATE)/emitter.tag
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# gen-opcodes
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GEN_OPCODES_TOOL = $(SOURCE_DIR)/ir/be/scripts/generate_new_opcodes.pl
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$(GEN_BE_DIR_ARM)/opcodes.tag:		$(GEN_OPCODES_TOOL) $(GEN_SPEC_ARM) tree.tag
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	$(GEN_OPCODES_TOOL) $(GEN_SPEC_ARM) $(GEN_BE_DIR_ARM)
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	touch $@
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$(GEN_BE_DIR_AMD64)/opcodes.tag:	$(GEN_OPCODES_TOOL) $(GEN_SPEC_AMD64) tree.tag
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	$(GEN_OPCODES_TOOL) $(GEN_SPEC_AMD64) $(GEN_BE_DIR_AMD64)
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	touch $@
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$(GEN_BE_DIR_IA32)/opcodes.tag:		$(GEN_OPCODES_TOOL) $(GEN_SPEC_IA32) tree.tag
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	$(GEN_OPCODES_TOOL) $(GEN_SPEC_IA32) $(GEN_BE_DIR_IA32)
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	touch $@
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$(GEN_BE_DIR_SPARC)/opcodes.tag:	$(GEN_OPCODES_TOOL) $(GEN_SPEC_SPARC) tree.tag
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	$(GEN_OPCODES_TOOL) $(GEN_SPEC_SPARC) $(GEN_BE_DIR_SPARC)
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	touch $@
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$(GEN_BE_DIR_TEMPLATE)/opcodes.tag:	$(GEN_OPCODES_TOOL) $(GEN_SPEC_TEMPLATE) tree.tag
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	$(GEN_OPCODES_TOOL) $(GEN_SPEC_TEMPLATE) $(GEN_BE_DIR_TEMPLATE)
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	touch $@
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$(GEN_BE_DIR_ARM)/gen_arm_new_nodes.c:		$(GEN_BE_DIR_ARM)/opcodes.tag
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$(GEN_BE_DIR_ARM)/gen_arm_new_nodes.h:		$(GEN_BE_DIR_ARM)/opcodes.tag
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$(GEN_BE_DIR_AMD64)/gen_amd64_new_nodes.c:	$(GEN_BE_DIR_AMD64)/opcodes.tag
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$(GEN_BE_DIR_AMD64)/gen_amd64_new_nodes.h:	$(GEN_BE_DIR_AMD64)/opcodes.tag
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$(GEN_BE_DIR_IA32)/gen_ia32_new_nodes.c:	$(GEN_BE_DIR_IA32)/opcodes.tag
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$(GEN_BE_DIR_IA32)/gen_ia32_new_nodes.h:	$(GEN_BE_DIR_IA32)/opcodes.tag
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$(GEN_BE_DIR_SPARC)/gen_sparc_new_nodes.c:	$(GEN_BE_DIR_SPARC)/opcodes.tag
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$(GEN_BE_DIR_SPARC)/gen_sparc_new_nodes.h:	$(GEN_BE_DIR_SPARC)/opcodes.tag
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$(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_new_nodes.c:	$(GEN_BE_DIR_TEMPLATE)/opcodes.tag
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$(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_new_nodes.h:	$(GEN_BE_DIR_TEMPLATE)/opcodes.tag
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# gen-regalloc
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GEN_REGALLOC_TOOL = $(SOURCE_DIR)/ir/be/scripts/generate_regalloc_if.pl
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$(GEN_BE_DIR_ARM)/regalloc.tag:		$(GEN_REGALLOC_TOOL) $(GEN_SPEC_ARM) tree.tag
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	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_ARM) $(GEN_BE_DIR_ARM)
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	touch $@
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$(GEN_BE_DIR_AMD64)/regalloc.tag:	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_AMD64) tree.tag
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	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_AMD64) $(GEN_BE_DIR_AMD64)
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	touch $@
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$(GEN_BE_DIR_IA32)/regalloc.tag:	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_IA32) tree.tag
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	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_IA32) $(GEN_BE_DIR_IA32)
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	touch $@
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$(GEN_BE_DIR_SPARC)/regalloc.tag:	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_SPARC) tree.tag
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	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_SPARC) $(GEN_BE_DIR_SPARC)
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	touch $@
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$(GEN_BE_DIR_TEMPLATE)/regalloc.tag:	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_TEMPLATE) tree.tag
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	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_TEMPLATE) $(GEN_BE_DIR_TEMPLATE)
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	touch $@
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$(GEN_BE_DIR_ARM)/gen_arm_regalloc_if.c:	$(GEN_BE_DIR_ARM)/regalloc.tag
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$(GEN_BE_DIR_ARM)/gen_arm_regalloc_if.h:	$(GEN_BE_DIR_ARM)/regalloc.tag
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$(GEN_BE_DIR_AMD64)/gen_amd64_regalloc_if.c:	$(GEN_BE_DIR_AMD64)/regalloc.tag
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$(GEN_BE_DIR_AMD64)/gen_amd64_regalloc_if.h:	$(GEN_BE_DIR_AMD64)/regalloc.tag
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$(GEN_BE_DIR_IA32)/gen_ia32_regalloc_if.c:	$(GEN_BE_DIR_IA32)/regalloc.tag
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$(GEN_BE_DIR_IA32)/gen_ia32_regalloc_if.h:	$(GEN_BE_DIR_IA32)/regalloc.tag
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$(GEN_BE_DIR_SPARC)/gen_sparc_regalloc_if.c:	$(GEN_BE_DIR_SPARC)/regalloc.tag
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$(GEN_BE_DIR_SPARC)/gen_sparc_regalloc_if.h:	$(GEN_BE_DIR_SPARC)/regalloc.tag
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$(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_regalloc_if.c:	$(GEN_BE_DIR_TEMPLATE)/regalloc.tag
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$(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_regalloc_if.h:	$(GEN_BE_DIR_TEMPLATE)/regalloc.tag
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# gen-all
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gen-ir:			$(GEN_IR_SRCS) $(GEN_IR_HEADERS)
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gen-emitter:		$(GEN_EMITTER_SRCS) $(GEN_EMITTER_HEADERS)
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gen-opcodes:		$(GEN_OPCODES_SRCS) $(GEN_OPCODES_HEADERS)
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gen-regalloc:		$(GEN_REGALLOC_SRCS) $(GEN_REGALLOC_HEADERS)
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gen-all:		gen-ir gen-emitter gen-opcodes gen-regalloc
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gen.tag:		$(GEN_ALL)
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			touch gen.tag
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gen:			gen.tag
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.PHONY:	clean-gen \
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	gen gen-all \
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	gen-ir gen-emitter gen-opcodes gen-regalloc