Blame project/codegen.mk

f98ae1
clean:		clean-gen
f98ae1
f98ae1
clean-gen:
f98ae1
		rm -f gen.tag
f98ae1
		rm -f $(GEN_IR_SRCS)
f98ae1
		rm -f $(GEN_IR_HEADERS)
a5e4b0
		rm -f $(GEN_EMITTER_SRCS)
a5e4b0
		rm -f $(GEN_EMITTER_HEADERS)
e685cd
		rm -f $(GEN_OPCODES_SRCS)
e685cd
		rm -f $(GEN_OPCODES_HEADERS)
9b9d84
		rm -f $(GEN_REGALLOC_SRCS)
9b9d84
		rm -f $(GEN_REGALLOC_HEADERS)
a5e4b0
		rm -f $(GEN_BE_DIR_ARM)/emitter.tag
a5e4b0
		rm -f $(GEN_BE_DIR_AMD64)/emitter.tag
a5e4b0
		rm -f $(GEN_BE_DIR_IA32)/emitter.tag
c461ed
		rm -f $(GEN_BE_DIR_MIPS)/emitter.tag
a5e4b0
		rm -f $(GEN_BE_DIR_SPARC)/emitter.tag
a5e4b0
		rm -f $(GEN_BE_DIR_TEMPLATE)/emitter.tag
e685cd
		rm -f $(GEN_BE_DIR_ARM)/opcodes.tag
e685cd
		rm -f $(GEN_BE_DIR_AMD64)/opcodes.tag
e685cd
		rm -f $(GEN_BE_DIR_IA32)/opcodes.tag
c461ed
		rm -f $(GEN_BE_DIR_MIPS)/opcodes.tag
e685cd
		rm -f $(GEN_BE_DIR_SPARC)/opcodes.tag
e685cd
		rm -f $(GEN_BE_DIR_TEMPLATE)/opcodes.tag
9b9d84
		rm -f $(GEN_BE_DIR_ARM)/regalloc.tag
9b9d84
		rm -f $(GEN_BE_DIR_AMD64)/regalloc.tag
9b9d84
		rm -f $(GEN_BE_DIR_IA32)/regalloc.tag
c461ed
		rm -f $(GEN_BE_DIR_MIPS)/regalloc.tag
9b9d84
		rm -f $(GEN_BE_DIR_SPARC)/regalloc.tag
9b9d84
		rm -f $(GEN_BE_DIR_TEMPLATE)/regalloc.tag
f98ae1
f98ae1
GEN_ALL 	= $(GEN_IR_SRCS) \
f98ae1
		  $(GEN_IR_HEADERS) \
a5e4b0
		  $(GEN_EMITTER_SRCS) \
a5e4b0
		  $(GEN_EMITTER_HEADERS) \
e685cd
		  $(GEN_OPCODES_SRCS) \
e685cd
		  $(GEN_OPCODES_HEADERS) \
9b9d84
		  $(GEN_REGALLOC_SRCS) \
9b9d84
		  $(GEN_REGALLOC_HEADERS) \
a5e4b0
a5e4b0
a5e4b0
# build/gen/ir/be
a5e4b0
GEN_BE_DIR_ARM		= build/gen/ir/be/arm
a5e4b0
GEN_BE_DIR_AMD64	= build/gen/ir/be/amd64
a5e4b0
GEN_BE_DIR_IA32		= build/gen/ir/be/ia32
c461ed
GEN_BE_DIR_MIPS		= build/gen/ir/be/mips
a5e4b0
GEN_BE_DIR_SPARC	= build/gen/ir/be/sparc
a5e4b0
GEN_BE_DIR_TEMPLATE	= build/gen/ir/be/TEMPLATE
a5e4b0
a5e4b0
GEN_SPEC_ARM		= $(SOURCE_DIR)/ir/be/arm/arm_spec.pl
a5e4b0
GEN_SPEC_AMD64		= $(SOURCE_DIR)/ir/be/amd64/amd64_spec.pl
a5e4b0
GEN_SPEC_IA32		= $(SOURCE_DIR)/ir/be/ia32/ia32_spec.pl
c461ed
GEN_SPEC_MIPS		= $(SOURCE_DIR)/ir/be/mips/mips_spec.pl
a5e4b0
GEN_SPEC_SPARC		= $(SOURCE_DIR)/ir/be/sparc/sparc_spec.pl
a5e4b0
GEN_SPEC_TEMPLATE	= $(SOURCE_DIR)/ir/be/TEMPLATE/TEMPLATE_spec.pl
f98ae1
f98ae1
f98ae1
# gen-ir
f98ae1
GEN_IR_TOOL = $(SOURCE_DIR)/scripts/gen_ir.py
f98ae1
GEN_IR_SPEC = $(SOURCE_DIR)/scripts/ir_spec.py
f98ae1
f98ae1
f98ae1
build/gen/ir/ir/%.c:	$(SOURCE_DIR)/scripts/templates/%.c \
f98ae1
			$(GEN_IR_TOOL) $(GEN_IR_SPEC) tree.tag
f98ae1
	$(GEN_IR_TOOL) $(GEN_IR_SPEC) $< > $@
f98ae1
f98ae1
f98ae1
build/gen/ir/ir/%.h:	$(SOURCE_DIR)/scripts/templates/%.h \
f98ae1
			$(GEN_IR_TOOL) $(GEN_IR_SPEC) tree.tag
f98ae1
	$(GEN_IR_TOOL) $(GEN_IR_SPEC) $< > $@
f98ae1
f98ae1
f98ae1
build/gen/include/libfirm/nodes.h:	$(SOURCE_DIR)/scripts/templates/nodes.h \
f98ae1
					$(GEN_IR_TOOL) $(GEN_IR_SPEC) tree.tag
f98ae1
	$(GEN_IR_TOOL) $(GEN_IR_SPEC) $< > $@
f98ae1
f98ae1
f98ae1
a5e4b0
# gen-emitter
a5e4b0
GEN_EMITTER_TOOL = $(SOURCE_DIR)/ir/be/scripts/generate_emitter.pl
a5e4b0
a5e4b0
6fdde6
$(GEN_BE_DIR_ARM)/emitter.tag:		$(GEN_EMITTER_TOOL) $(GEN_SPEC_ARM) tree.tag
a5e4b0
	$(GEN_EMITTER_TOOL) $(GEN_SPEC_ARM) $(GEN_BE_DIR_ARM)
a5e4b0
	touch $@
a5e4b0
a5e4b0
6fdde6
$(GEN_BE_DIR_AMD64)/emitter.tag:	$(GEN_EMITTER_TOOL) $(GEN_SPEC_AMD64) tree.tag
a5e4b0
	$(GEN_EMITTER_TOOL) $(GEN_SPEC_AMD64) $(GEN_BE_DIR_AMD64)
a5e4b0
	touch $@
a5e4b0
a5e4b0
6fdde6
$(GEN_BE_DIR_IA32)/emitter.tag:		$(GEN_EMITTER_TOOL) $(GEN_SPEC_IA32) tree.tag
a5e4b0
	$(GEN_EMITTER_TOOL) $(GEN_SPEC_IA32) $(GEN_BE_DIR_IA32)
a5e4b0
	touch $@
a5e4b0
a5e4b0
c461ed
$(GEN_BE_DIR_MIPS)/emitter.tag:		$(GEN_EMITTER_TOOL) $(GEN_SPEC_MIPS) tree.tag
c461ed
	$(GEN_EMITTER_TOOL) $(GEN_SPEC_MIPS) $(GEN_BE_DIR_MIPS)
c461ed
	touch $@
c461ed
c461ed
6fdde6
$(GEN_BE_DIR_SPARC)/emitter.tag:	$(GEN_EMITTER_TOOL) $(GEN_SPEC_SPARC) tree.tag
a5e4b0
	$(GEN_EMITTER_TOOL) $(GEN_SPEC_SPARC) $(GEN_BE_DIR_SPARC)
a5e4b0
	touch $@
a5e4b0
a5e4b0
6fdde6
$(GEN_BE_DIR_TEMPLATE)/emitter.tag:	$(GEN_EMITTER_TOOL) $(GEN_SPEC_TEMPLATE) tree.tag
a5e4b0
	$(GEN_EMITTER_TOOL) $(GEN_SPEC_TEMPLATE) $(GEN_BE_DIR_TEMPLATE)
a5e4b0
	touch $@
a5e4b0
a5e4b0
a5e4b0
a5e4b0
$(GEN_BE_DIR_ARM)/gen_arm_emitter.c:		$(GEN_BE_DIR_ARM)/emitter.tag
a5e4b0
$(GEN_BE_DIR_ARM)/gen_arm_emitter.h:		$(GEN_BE_DIR_ARM)/emitter.tag
a5e4b0
a5e4b0
$(GEN_BE_DIR_AMD64)/gen_amd64_emitter.c:	$(GEN_BE_DIR_AMD64)/emitter.tag
a5e4b0
$(GEN_BE_DIR_AMD64)/gen_amd64_emitter.h:	$(GEN_BE_DIR_AMD64)/emitter.tag
a5e4b0
a5e4b0
$(GEN_BE_DIR_IA32)/gen_ia32_emitter.c:		$(GEN_BE_DIR_IA32)/emitter.tag
a5e4b0
$(GEN_BE_DIR_IA32)/gen_ia32_emitter.h:		$(GEN_BE_DIR_IA32)/emitter.tag
a5e4b0
c461ed
$(GEN_BE_DIR_MIPS)/gen_mips_emitter.c:		$(GEN_BE_DIR_MIPS)/emitter.tag
c461ed
$(GEN_BE_DIR_MIPS)/gen_mips_emitter.h:		$(GEN_BE_DIR_MIPS)/emitter.tag
c461ed
a5e4b0
$(GEN_BE_DIR_SPARC)/gen_sparc_emitter.c:	$(GEN_BE_DIR_SPARC)/emitter.tag
a5e4b0
$(GEN_BE_DIR_SPARC)/gen_sparc_emitter.h:	$(GEN_BE_DIR_SPARC)/emitter.tag
a5e4b0
a5e4b0
$(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_emitter.c:	$(GEN_BE_DIR_TEMPLATE)/emitter.tag
a5e4b0
$(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_emitter.h:	$(GEN_BE_DIR_TEMPLATE)/emitter.tag
a5e4b0
a5e4b0
a5e4b0
e685cd
# gen-opcodes
e685cd
GEN_OPCODES_TOOL = $(SOURCE_DIR)/ir/be/scripts/generate_new_opcodes.pl
e685cd
e685cd
6fdde6
$(GEN_BE_DIR_ARM)/opcodes.tag:		$(GEN_OPCODES_TOOL) $(GEN_SPEC_ARM) tree.tag
e685cd
	$(GEN_OPCODES_TOOL) $(GEN_SPEC_ARM) $(GEN_BE_DIR_ARM)
e685cd
	touch $@
e685cd
e685cd
6fdde6
$(GEN_BE_DIR_AMD64)/opcodes.tag:	$(GEN_OPCODES_TOOL) $(GEN_SPEC_AMD64) tree.tag
e685cd
	$(GEN_OPCODES_TOOL) $(GEN_SPEC_AMD64) $(GEN_BE_DIR_AMD64)
e685cd
	touch $@
e685cd
e685cd
6fdde6
$(GEN_BE_DIR_IA32)/opcodes.tag:		$(GEN_OPCODES_TOOL) $(GEN_SPEC_IA32) tree.tag
e685cd
	$(GEN_OPCODES_TOOL) $(GEN_SPEC_IA32) $(GEN_BE_DIR_IA32)
e685cd
	touch $@
e685cd
e685cd
c461ed
$(GEN_BE_DIR_MIPS)/opcodes.tag:		$(GEN_OPCODES_TOOL) $(GEN_SPEC_MIPS) tree.tag
c461ed
	$(GEN_OPCODES_TOOL) $(GEN_SPEC_MIPS) $(GEN_BE_DIR_MIPS)
c461ed
	touch $@
c461ed
c461ed
6fdde6
$(GEN_BE_DIR_SPARC)/opcodes.tag:	$(GEN_OPCODES_TOOL) $(GEN_SPEC_SPARC) tree.tag
e685cd
	$(GEN_OPCODES_TOOL) $(GEN_SPEC_SPARC) $(GEN_BE_DIR_SPARC)
e685cd
	touch $@
e685cd
e685cd
6fdde6
$(GEN_BE_DIR_TEMPLATE)/opcodes.tag:	$(GEN_OPCODES_TOOL) $(GEN_SPEC_TEMPLATE) tree.tag
e685cd
	$(GEN_OPCODES_TOOL) $(GEN_SPEC_TEMPLATE) $(GEN_BE_DIR_TEMPLATE)
e685cd
	touch $@
e685cd
e685cd
e685cd
e685cd
$(GEN_BE_DIR_ARM)/gen_arm_new_nodes.c:		$(GEN_BE_DIR_ARM)/opcodes.tag
e685cd
$(GEN_BE_DIR_ARM)/gen_arm_new_nodes.h:		$(GEN_BE_DIR_ARM)/opcodes.tag
e685cd
e685cd
$(GEN_BE_DIR_AMD64)/gen_amd64_new_nodes.c:	$(GEN_BE_DIR_AMD64)/opcodes.tag
e685cd
$(GEN_BE_DIR_AMD64)/gen_amd64_new_nodes.h:	$(GEN_BE_DIR_AMD64)/opcodes.tag
e685cd
e685cd
$(GEN_BE_DIR_IA32)/gen_ia32_new_nodes.c:	$(GEN_BE_DIR_IA32)/opcodes.tag
e685cd
$(GEN_BE_DIR_IA32)/gen_ia32_new_nodes.h:	$(GEN_BE_DIR_IA32)/opcodes.tag
e685cd
c461ed
$(GEN_BE_DIR_MIPS)/gen_mips_new_nodes.c:	$(GEN_BE_DIR_MIPS)/opcodes.tag
c461ed
$(GEN_BE_DIR_MIPS)/gen_mips_new_nodes.h:	$(GEN_BE_DIR_MIPS)/opcodes.tag
c461ed
e685cd
$(GEN_BE_DIR_SPARC)/gen_sparc_new_nodes.c:	$(GEN_BE_DIR_SPARC)/opcodes.tag
e685cd
$(GEN_BE_DIR_SPARC)/gen_sparc_new_nodes.h:	$(GEN_BE_DIR_SPARC)/opcodes.tag
e685cd
e685cd
$(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_new_nodes.c:	$(GEN_BE_DIR_TEMPLATE)/opcodes.tag
e685cd
$(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_new_nodes.h:	$(GEN_BE_DIR_TEMPLATE)/opcodes.tag
e685cd
e685cd
e685cd
9b9d84
# gen-regalloc
9b9d84
GEN_REGALLOC_TOOL = $(SOURCE_DIR)/ir/be/scripts/generate_regalloc_if.pl
9b9d84
9b9d84
6fdde6
$(GEN_BE_DIR_ARM)/regalloc.tag:		$(GEN_REGALLOC_TOOL) $(GEN_SPEC_ARM) tree.tag
9b9d84
	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_ARM) $(GEN_BE_DIR_ARM)
9b9d84
	touch $@
9b9d84
9b9d84
6fdde6
$(GEN_BE_DIR_AMD64)/regalloc.tag:	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_AMD64) tree.tag
9b9d84
	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_AMD64) $(GEN_BE_DIR_AMD64)
9b9d84
	touch $@
9b9d84
9b9d84
6fdde6
$(GEN_BE_DIR_IA32)/regalloc.tag:	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_IA32) tree.tag
9b9d84
	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_IA32) $(GEN_BE_DIR_IA32)
9b9d84
	touch $@
9b9d84
9b9d84
c461ed
$(GEN_BE_DIR_MIPS)/regalloc.tag:	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_MIPS) tree.tag
c461ed
	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_MIPS) $(GEN_BE_DIR_MIPS)
c461ed
	touch $@
c461ed
c461ed
6fdde6
$(GEN_BE_DIR_SPARC)/regalloc.tag:	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_SPARC) tree.tag
9b9d84
	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_SPARC) $(GEN_BE_DIR_SPARC)
9b9d84
	touch $@
9b9d84
9b9d84
6fdde6
$(GEN_BE_DIR_TEMPLATE)/regalloc.tag:	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_TEMPLATE) tree.tag
9b9d84
	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_TEMPLATE) $(GEN_BE_DIR_TEMPLATE)
9b9d84
	touch $@
9b9d84
9b9d84
9b9d84
9b9d84
$(GEN_BE_DIR_ARM)/gen_arm_regalloc_if.c:	$(GEN_BE_DIR_ARM)/regalloc.tag
9b9d84
$(GEN_BE_DIR_ARM)/gen_arm_regalloc_if.h:	$(GEN_BE_DIR_ARM)/regalloc.tag
9b9d84
9b9d84
$(GEN_BE_DIR_AMD64)/gen_amd64_regalloc_if.c:	$(GEN_BE_DIR_AMD64)/regalloc.tag
9b9d84
$(GEN_BE_DIR_AMD64)/gen_amd64_regalloc_if.h:	$(GEN_BE_DIR_AMD64)/regalloc.tag
9b9d84
9b9d84
$(GEN_BE_DIR_IA32)/gen_ia32_regalloc_if.c:	$(GEN_BE_DIR_IA32)/regalloc.tag
9b9d84
$(GEN_BE_DIR_IA32)/gen_ia32_regalloc_if.h:	$(GEN_BE_DIR_IA32)/regalloc.tag
9b9d84
c461ed
$(GEN_BE_DIR_MIPS)/gen_mips_regalloc_if.c:	$(GEN_BE_DIR_MIPS)/regalloc.tag
c461ed
$(GEN_BE_DIR_MIPS)/gen_mips_regalloc_if.h:	$(GEN_BE_DIR_MIPS)/regalloc.tag
c461ed
9b9d84
$(GEN_BE_DIR_SPARC)/gen_sparc_regalloc_if.c:	$(GEN_BE_DIR_SPARC)/regalloc.tag
9b9d84
$(GEN_BE_DIR_SPARC)/gen_sparc_regalloc_if.h:	$(GEN_BE_DIR_SPARC)/regalloc.tag
9b9d84
9b9d84
$(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_regalloc_if.c:	$(GEN_BE_DIR_TEMPLATE)/regalloc.tag
9b9d84
$(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_regalloc_if.h:	$(GEN_BE_DIR_TEMPLATE)/regalloc.tag
9b9d84
9b9d84
9b9d84
f98ae1
# gen-all
f98ae1
gen-ir:			$(GEN_IR_SRCS) $(GEN_IR_HEADERS)
f98ae1
a5e4b0
gen-emitter:		$(GEN_EMITTER_SRCS) $(GEN_EMITTER_HEADERS)
a5e4b0
e685cd
gen-opcodes:		$(GEN_OPCODES_SRCS) $(GEN_OPCODES_HEADERS)
e685cd
9b9d84
gen-regalloc:		$(GEN_REGALLOC_SRCS) $(GEN_REGALLOC_HEADERS)
9b9d84
9b9d84
gen-all:		gen-ir gen-emitter gen-opcodes gen-regalloc
f98ae1
f98ae1
gen.tag:		$(GEN_ALL)
f98ae1
			touch gen.tag
f98ae1
f98ae1
gen:			gen.tag
f98ae1
f98ae1
f98ae1
.PHONY:	clean-gen \
f98ae1
	gen gen-all \
9b9d84
	gen-ir gen-emitter gen-opcodes gen-regalloc